Dr. Manjith B.C.

Assistant Professor
Indian Institute of Information Technology Kottayam
Valavoor P.O, Pala
Kottayam - 686635, Kerala, India.
Email: manjithbc at iiitkottayam dot ac.in
Hello at: 00 91 04822202172

Research Interests :

• Reconfigurable Computing
• Hardware Security
• FPGA
• Cryptographic Engines
• Evolvable Hardware
• ML in security

Education :

• Ph.D, Computer Science and Engineering, Thesis titled: “Enhancing Performance of FPGA based AES implementations for improved security”, National Institute of Technology Tiruchirappalli, 2018.
• M.Tech., Computer Science and Engineering, Anna University, 2009.
• B.Tech, Computer Science and Engineering, Kerala University, 2007.

Ongoing research works

• IoT security and Lightweight Cryptography.
• Intrusion detection system using deep learning approach.
• Protecting FPGA IP core using tamper proof logic locking method.
• Hardware/Software co-designs.
• ML in security.
• Secure Memory design.
• Logic locking for FPGA IP protection.

Research and Consultancy

We obtained project funding for ”SecAI HSM- Machine Learning based malware and botnet prevention Hardware Security Module on Unmanned Aerial Vehicles” worth Rs. 27 lakhs from C3iHub, IIT Kanpur.

Received S$12,000 Sponsorship for collaboration on “6G TERACOMM SoC project” from TeraX Labs, Nanyang Technological University, Singapore.

Patent Granted

• Filed patent : IoT based Real-Time monitoring system for bridge safety and water quality assessment in Flood-Prone, Application number- 202541073773.
• Patent Title: Logic encryption decryption system for protecting hardware circuits and method thereof
  Patent Number: 430767
  Date of Patent Grant: 01-05-2023
  Patent Issuing Authority: Indian Patent Office
  Inventors: N.Ramasubramanian, Manjith B.C.
  Brief Description: The patented system enables FPGA designers and IP owners to safeguard their valuable intellectual property from unauthorized usage or replication. The system utilizes a slice-based locking technique, which significantly enhances the protection of sensitive information and intellectual property embedded within the hardware circuits. By employing logic encryption, the system provides an additional layer of security, making it significantly more challenging for adversaries to reverse-engineer the design or extract sensitive information.

Publications

1. David, Aksa, and B. C. Manjith. "Comparative Analysis of Timing Parameters in Reconfigurable Devices." 2025 International Conference on Advancements in Power, Communication and Intelligent Systems (APCI). IEEE, 2025.
2. Halder, Saptarsi, and Manjith Baby Sarojam Chellam. "Dynamic Partial Reconfiguration for adaptive QKD key distillation process on FPGA." 2025 6th International Conference on Control, Communication and Computing (ICCC). IEEE, 2025.
3. David, Aksa, and B. C. Manjith. "Innovative Approaches to FPGA Security: Leveraging LUT Locking and Future Directions." 2024 International Conference on Smart Electronics and Communication Systems (ISENSE). IEEE, 2024.
4. Chellam, Manjith Baby Sarojam, Ramasubramanian Natarajan, and Nagi Naganathan. “Logic locking emulator on FPGA: A conceptual view”. In: 2024 37th International Conference on VLSI De sign and 2024 23rd International Conference on Embedded Systems (VLSID). IEEE. 2024, pp. 553– 559.
5. Manjith Baby Sarojam Chellam, Ramasubramanian Natarajan, and Nagi Naganathan, “Secure key exchange protocol and storage of logic locking key” in 28th International Symposium on VLSI Design and Test (VDAT-2024).
6. Akash, Tej, et al. "Identifying Insider Cyber Threats Using Behaviour Modelling and Analysis." 2023 OITS International Conference on Information Technology (OCIT). IEEE, 2023.
7. Faseela, M. H., and B. C. Manjith. "A Survey on Eliminating Botnet and Intrusion Attacks Through Machine Learning." 2023 Innovations in Power and Advanced Computing Technologies (i-PACT) (2023): 1-9.
8. Manjith, B. C., and R. Dhanalakshmi. "A framework for data and device protection on mobile devices using logic encryption." International Journal of Business Information Systems 43.3 (2023): 416-428.
9. Manjith B.C., N. Ramasubramanian, “AES Hardware Accelerator on FPGA with Improved Throughput and Resource Efficiency”, Arabian Journal for Science and Engineering, springer, Vol.43, Issue 12.
10. Manjith, B. C., and R. Dhanalakshmi. "Enabling self-adaptability of small scale and large scale security systems using dynamic partial reconfiguration." Journal of Ambient Intelligence and Humanized Computing 12 (2021): 9387-9403.
11. Manjith B.C., N. Ramasubramanian, “Securing AES Accelerator from Key-Leaking Trojans on FPGA”, International Journal of Embedded and Real-Time Communication Systems, Vol.11, Issue 3.
12. Manjith B.C., “Improving Correctness of Logic Circuit Using Self-Healing Built-In Logic Test module in FPGA using Dynamic Partial Reconfiguration”, International Journal of Recent Technology and Engineering, Vol.8 Issue 2.
13. Manjith B.C., “Hardware evolution of AES algorithm on FPGA”, 2019 Innovations in Power and Advanced Computing Technologies (i-PACT) conference, IEEE digital Library.
14. Manjith B.C., “Improving overall parallelism in AES accelerator using BRAM and multiple input blocks”, 2019 Innovations in Power and Advanced Computing Technologies (i-PACT) conference, IEEE digital Library.
15. Manjith B.C., J.Kokila, N.Ramasubramanian, “Adaptive Dynamic Partial Reconfigurable Security System” International Conference on Next Generation Computing Technologies. Springer, Singapore, 2017.
16. J.Koila, Manjith B.C., N.Ramasubramanian, “Light Weight Two-Factor Authentication Using Hybrid PUF and FSM for SOC FPGA”, International Conference on Next Generation Computing Technologies. Springer, Singapore, 2017.
17. Manjith B.C., N. Ramasubramanian, “A Survey of Hardware - Software Security Architectures to Cloud Server”, ICCN-2014 Elsevier Conference.
18. CP, Sandhya, and Manjith BC. "Analysis of Security Issues, Threats and Challenges in Cyber–Physical System for IoT Devices." Proceedings of the International Conference on IoT Based Control Networks & Intelligent Systems-ICICNIS. 2021.

Book Chapter

1. N. Ramasubramanian, Manjith B.C., Cryptographic engines for cloud based on FPGA; IET 2019 book “Authentication Technologies for Cloud Technology, IoT, and Big Data”, ISBN: 978-1-78561-556-6, pp. 273-308.
2. Sandhya, C. P., and B. C. Manjith. "Challenging Aspects of Data Preserving Algorithms in IoT Enabled Smart Societies." Society 5.0: Smart Future Towards Enhancing the Quality of Society. Singapore: Springer Nature Singapore, 2022. 87-111.

Invited Talks

1. Delivered a talk on "Security Protocols implementation with FPGA" in Science and Engineering Research Board (SERB) Sponsored One Week High–End Workshop on “SDN: Software Defined Networks Architectures and Applications” on 17 – 23 July 2023.
2. Invited speaker for a talk on "Hardware Security" at the Five Days Workshop on Advanced Cryptography and Digital Forensics held from 5th June to 9th June, 2023 at IIIT Kottayam .
3. Panel discussion member on "Incident response plan for working professionals" as part of Colloquium '23 conducted by IEEE Computer Society Kerala chapter.
4. Invited talk in five-day online faculty development program on "Cyber security and Blockchain Technology" organized by the Department of Computer Science and Engineering, IIIT Bhagalpur, India.
5. Keynote speaker at the International Conference on Computational Intelligence and Digital Technologies, organized by Mangalam College of Engineering, Kerala, India.
6. Invited talk in ATAL sponsored five-day online faculty development program on "Cyber security and Digital Forensic" organized by the Department of Computer Science and Engineering, IIIT Kottayam, India.

Ph.D. Students

1. Ms. Sandhya C.P.(2020PHD11006)
   Area of Research: Lightweight Cryptography
2. Ms. Faseela M.H.(2022PHD21004)
   Area of Research: Machine Learning in Cybersecurity
3. Ms. Aksa David ( 2023PHD11012)
   Area of Research: Hardware Security
4. Ms.Sruthy Sebastian (2025PHD11003)
   Area of Research: Cybersecurity in Autonomous and unmanned Ariel Vehicles

Undergraduate Projects Guided

• Title: Behaviour Modelling: Using User Behaviour to Identify Employees With Malicious Intent or Identity Theft.
  Students List: Alaka Jayan Choorappetty (2019bcs0044), Teeparti Tejakash (2019bcs0062), Saddikuti Vishnu Vardhan R (2019BCS0074), Nimit Gaur (2019BCS0043)
  Academic Year: 2022-2023
• Title: Pulmonary Disease Detection: A Deep Learning Way
  Student Name: Mahesh Vanam (2019BCS0030)
  Academic Year: 2022-2023
• Title: An Efficient Approach for Raytracing in CUDA and NVIDIA Opti XEngine Using Quincunx Anti-aliasing
  Students List: Antony Francis (2018bcs0007), Muhammed Nizar E(Muhammed Nizar E ), Vaisakh Dileep( 2018BCS0077)
  Academic Year: 2021-2022
• Title: Location Tracking of VoIP Calls
  Student Name: Muhammed Nizar E (2018BCS0038)
  Academic Year: 2021-2022
• Title: Hate Speech Detection on in Social Media
  Student Name: ADHYAN (2017BCS0003)
  Academic Year: 2020-2021
• Title: Car Price Prediction
  Student Name: Rahul Kumar Singh (2017BCS0045)
  Academic Year: 2020-2021
• Title: Voice-Based Email System Using AI
  Student Name: Somesh Kumar (2017BCS0058)
  Academic Year: 2020-2021
• Title: Stock Market Prediction Using Artificial Neural Network
  Student Name: Anshuman Gaurav (2017BCS0007)
  Academic Year: 2020-2021

Courses Taught at IIITK

• IT Workshop-II
• IT Workshop-III
• Operating System
• Machine Learning
• Cryptography and Network Security
• Object Oriented Analysis and Design
• Machine Learning in Cybersecurity

Events Organized

• Organized three days workshop on “Xilinx FPGA Board Workshop: From Basics to Advanced” at Indian Institute of Information Technology Kottayam from 13 to 15 October 2023(Offline).
• Organized Cyber Security Series of Webinar- I at Indian Institute of Information Technology Kottayam from 12.11.2021 to 14.11.2021.
• Organized Cyber Security Series of Webinar- II at Indian Institute of Information Technology Kottayam on 20.11.2021.
• Organized seminar on PYNQ- Python Productivity at Indian Institute of Information Technology Kottayam on ZYNQ on 13.07.2020.
• PY NQ- Python Productivity on ZYNQ on 13.07.2020
• Cyber Security Series of Webinar- I on 12.11.2021 to 14.11.2021
• Cyber Security Series of Webinar- II on 20.11.2021

Professional Activities

Reviewer:

• IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
• Reviewer of The computer Journal-Oxford academics.
• Reviewer of Journal of Circuits, Systems, and Computers (JCSC).
• Reviewer of Computer Systems Science and Engineering.
• Reviewer of International Conference on intelligent COMPUting TEchnologies and Research (i-COMPUTER – 2023).
• Reviewer of AMHM-2023: Handbook of AI-Based Models in Healthcare and Medicine: Approaches, Theories, and Applications.

Secure reProgrammable Hardware INfrastructure ReXearch (SPHINX) Lab

The Secure reProgrammable Hardware Infrastructure ReXearch (SPHINX) Lab is at the forefront of innovative research in the realms of hardware security, FPGA-based designs, and cybersecurity. Our mission is to advance the state-of-the-art in secure and efficient hardware systems through interdisciplinary research that combines hardware design, machine learning, and cryptographic techniques.

SPHINX has received funding of Rs.27.67 Lakhs for the project titled "SecAI-HSM’: Machine Learning based malware and botnet prevention Hardware Security Module on Unmanned Aerial Vehicles (UAV)" funded by Cybersecurity and Cybersecurity of Cyber-physical Systems A Cybersecurity Technology Innovation Hub at IIT Kanpur. We received S$12,000 Sponsorship for collaboration on “6G TERACOMM SoC project” from TeraX Labs, Nanyang Technological University, Singapore. Additionally, SPHINX received travel grants for international collaboration with International Centre for Theoretical Physics (ICTP) Italy and New York University (NYU) Abu Dhabi.

Objectives:

1. Hardware Security:
• Threat Detection and Mitigation: Developing novel techniques to identify and counteract hardware-based attacks, including side-channel attacks and hardware Trojans
• Secure Design Practices: Creating methodologies and tools for designing inherently secure hardware components.


2. FPGA-Based Design:
• Reconfigurable Systems: Leveraging the flexibility of FPGAs to create adaptable and secure hardware solutions for various applications.
• High-Level Synthesis (HLS): Utilizing HLS tools to streamline the design and implementation of complex FPGA-based systems.


3. Cybersecurity:
• System Vulnerability Analysis: Investigating vulnerabilities in existing hardware and software systems to develop robust countermeasures.
• Secure Communication Protocols: Designing and implementing protocols to ensure secure data transmission across hardware platforms.


4. Application of ML on Hardware Security:
• Anomaly Detection: Using machine learning algorithms to detect abnormal behavior in hardware systems indicative of security breaches.
• Predictive Security Models: Employing ML models to predict potential security threats and proactively implement defenses.


5. ML Accelerators on FPGA:
• Efficient ML Implementations: Designing FPGA-based accelerators to enhance the performance and efficiency of machine learning models using hls4ml.
• Custom Architectures: Developing specialized hardware architectures tailored for specific ML tasks, optimizing both speed and power consumption.


6. Cryptography:
• Hardware-Optimized Cryptographic Algorithms: Implementing cryptographic algorithms on FPGA and other hardware platforms to ensure data security with minimal performance overhead.

Activities

• Research and Development Projects
• Collaborative Research Initiatives
• Workshops and Seminars
• Publications and Conferences
• Internship opportunities
• Grant Writing and Funding Acquisition

Sl. No.	Description	Part	Quantity
1	Xilinx Vivado ML Enterprise Edition (25 Users) with Vitis Model Composer Plugin (25 Users)	UEFVIVADOENTER-2s + UEFMATSIMADDON2S	1
2	Xilinx Zynq UltraScale + MPSoC ZCUI02 Evaluation Kit	EK-UI-ZCUI02-G	1
3	Xilinx Zynq UltraScale + MPSoC ZCUIO4 Evaluation Kit	EK-UI-ZCUIO4-G	1
4	RealDigital Boolean Board	Boolean	10
5	Basys 3 Artix-7 FPGA Trainer Board	410-183	10